A typical horizontal deflection circuit for a CRT includes a horizontal deflection winding of a deflection yoke coupled in parallel with a retrace capacitance provided by, for example, a retrace capacitor. A horizontal output or switching transistor operating at a horizontal deflection frequency is coupled across the retrace capacitor. A supply voltage is coupled to the switching transistor and to the retrace capacitor via a supply inductance.
For a given deflection winding inductance and a supply voltage magnitude, the effective retrace capacitance required to produce the same deflection current amplitude would have to be smaller when a higher deflection frequency is utilized than when a lower deflection frequency is utilized. Therefore, the flyback pulse voltage developed across a horizontal output transistor would have to be higher at the higher deflection frequency. For a given switching transistor breakdown voltage characteristic, the maximum flyback pulse voltage that is permitted to develop across a horizontal output transistor limits the allowable, maximum horizontal frequency that can be utilized. Therefore, it may be desirable to reduce the effective retrace capacitance without substantially increasing the flyback pulse voltage developed across the horizontal output transistor.
A horizontal deflection circuit, embodying an inventive feature, includes switched, first and second retrace capacitors coupled in series with a deflection winding. First and second switching transistors are coupled across the first and second retrace capacitors, respectively. A supply voltage is coupled via a supply inductance to a junction terminal between the retrace capacitors. The switching transistors are switched off, during retrace, to produce a first retrace pulse voltage across the first retrace capacitance and a second retrace pulse voltage across the second retrace capacitance. The retrace pulse voltage across the deflection winding is equal to the sum of a first retrace pulse voltage and the second retrace pulse voltage and is larger than each. The retrace pulse voltage across the deflection winding is proportional to a ratio of the capacitances of the first and second capacitances. Thereby, capacitive transformation is obtained. Similarly, a voltage across an S-shaping capacitor that is coupled in series with the deflection winding is also proportional to a ratio of the capacitances of the first and second capacitances.
Advantageously, the peak voltage developed across each of the switching transistors is substantially smaller than the sum retrace pulse voltage developed across the deflection winding. The result is that, for a given switching transistor breakdown voltage characteristic, the maximum scan frequency that can be employed is, advantageously, higher than in a deflection circuit in which the entire retrace pulse voltage across the deflection winding is developed across a single switching transistor.
A horizontal deflection circuit, embodying an inventive feature, includes an East-West raster distortion correction circuit for correcting pincushion raster distortion. Switched, first and second retrace capacitors are provided for providing the aforementioned capacitive transformation. Throughout a given vertical trace interval, the retrace switching timing of each one of the switching transistors remains the same relative to that of the other one of the switching transistors. Thereby, advantageously, East-West raster distortion correction is obtained in a manner that avoids producing retrace time modulation.
A video display deflection apparatus, embodying an inventive feature, includes a first retrace capacitance and a second retrace capacitance. A deflection winding is coupled to the first and second retrace capacitances to form a resonant circuit with the first and second retrace capacitances, during retrace. A first switching transistor is coupled to the first retrace capacitance for generating a first retrace pulse voltage in the resonant circuit. A second switching transistor is coupled to the second retrace capacitance for generating a second retrace pulse voltage in the second retrace capacitance. The first and second retrace pulse voltage are applied to the deflection winding in a manner to provide for retrace capacitance transformation. The second switching transistor is responsive to the first retrace pulse voltage for controlling, in accordance with the first retrace pulse voltage, when a switching operation occurs in the second switching transistor.